The present application relates to power semiconductor devices, and more particularly to vertical and lateral conduction devices which include immobile electric charge which statically inverts a semiconductor drift region.
Note that the points discussed below may reflect the hindsight gained from the disclosed inventions, and are not necessarily admitted to be prior art.
Power MOSFETs are widely used as switching devices in many electronic applications. In order to minimize the conduction power losses it is desirable that power MOSFETs have a low specific on-resistance (RSP or R*A), which is defined as the product of the on-resistance of the MOSFET multiplied by the active die area. In general, the on-resistance of a power MOSFET is dominated by the channel and drift region resistances.
Recently, inventions have been disclosed that incorporate fixed or permanent charges QF in trenches filled with dielectric material such as silicon oxide (SiO2). See for example US patent application 20080164518 which is hereby incorporated by reference. Positive permanent electrostatic charge can be formed within a device structure by, for example, implanting ions such as Cesium into a dielectric (such as SiO2).
FIG. 19 shows an example of such structures. In the MOSFET structure shown in FIG. 19 the gate electrode is formed in the same trench where the lower part is filled with a dielectric material that includes immobile positive electrostatic charge. The positive permanent charges balance the P layer's negative depletion charge in the off-state. The positive permanent charge also forms an induced electron drift region by forming an inversion layer along the interface between the oxide and the P layer. The induced inversion layer provides a path for electrons current flowing from the source and the channel to the drain.
In order to provide current continuity from the channel to the induced inversion layer, the gate electrode has to be in close proximity to the induced electron drift region. Therefore, special care is needed in fabricating such devices, in order to achieve both proper functionality and acceptable gate oxide reliability.